Problem with ADC on ULP RISC-V while deep-sleep

#1

Hi all,
I a trying to run this simple code, which use ADC on ULP.
The code should work and is working on other boards.

Specifically on Heltec_WiFi_LoRa_V3 board, it is being stuck on not finalizing the ADC conversation, and specifically waiting for the (bool)SENS.sar_meas1_ctrl2.meas1_done_sar bit to be ready.

Using ADC on the main CPU works fine, it is only over ULP, and only for this board.

Any idea why or how to overcome this?

Thanks!

#2

Heads-up that you will find approximately zero people here that can comment on anything ULP. You’re probably better off at the Espressif forum.

#3

Which “other” boards?

Can you review the schematics to see if there are any differences in implementation?

Why use the LoRa v3? What does it do the other boards don’t?

#4

Hi,
I am using also ESP32-S3-DevKitc-1. But I was wrong. I uploaded the same code to it and it is also not working. Something with ADC and ULP is not working well with ESP-IDF.