Hello @kater_s
Sorry about the missing parts:
you must include:
#include <cytypes.h>
#include <cyfitter.h>
#include <cydevice_trm.h>
#include <CyLib.h>
#if (CY_IP_SRSSLT)
#define HFCLK_DIVIDER (2u)
#else
#define HFCLK_DIVIDER (1u)
#endif
//#define CLK_IMO_MHZ (24u)
#define SYSCLK_DIVIDER (2u)
#define HZ_IN_MHZ (1000000u)
uint32 clkSelectReg; // save the system clock in mhz
as for changing the frequency yes you must update other things that affect the correct timing, i remember reading about this when i was digging for the info… that’s where the CyDelayFreq
does matches the right frequency with the correct timing… my settings might not be correct as this was done a while ago… so here are some of my notes from the project… please go through them and hopefully you will find the correct settings.
void setup()
{
clkSelectReg = CY_SYS_CLK_SELECT_REG; // 24 Mhz keep track of the current settings
// DEBUG_MSG(false, "\t\n Before clkSelectReg =%u", clkSelectReg);
// CySysClkWriteSysclkDiv(CY_SYS_CLK_SYSCLK_DIV1);
// DEBUG_MSG(false, "\t\n After clkSelectReg CY_SYS_CLK_SYSCLK_DIV1=%u", CY_SYS_CLK_SELECT_REG);
// CySysClkWriteSysclkDiv(CY_SYS_CLK_SYSCLK_DIV2);
// DEBUG_MSG(false, "\t\n After clkSelectReg CY_SYS_CLK_SYSCLK_DIV2=%u", CY_SYS_CLK_SELECT_REG);
// CySysClkWriteSysclkDiv(CY_SYS_CLK_SYSCLK_DIV4);
// DEBUG_MSG(false, "\t\n After clkSelectReg CY_SYS_CLK_SYSCLK_DIV4 <=12MHz=%u", CY_SYS_CLK_SELECT_REG);
// // Restore system clock configuration
// // CY_SYS_CLK_SELECT_REG = clkSelectReg;
// Internal low power oscillator is stopped as it is not used in this project
// CySysClkIloStop(); // This is actually already done in the clock settings in PSoC Creator, but this is how it is achieved in code.
// Set the divider for ECO, ECO will be used as source when IMO is switched off to save power
// CySysClkWriteEcoDiv(CY_SYS_CLK_ECO_DIV8); // --> Provides a 3 MHz clock. Lowest clock acceptable for SW Tx UART component.
// change HF clock source from IMO to ECO, as IMO is not required and can be stopped to save power
// CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_ECO);
// stop IMO for reducing power consumption
// CySysClkImoStop();
// CySysFlashSetWaitCycles can optionally be called after lowering SYSCLK
// clock frequency in order to improve the CPU performance.
// CySysFlashSetWaitCycles(3); // Frequency in MHz
// Update Delay frequency as clock frequency has changed
// CyDelayFreq(3000000UL);
// CySysClkWriteSysclkDiv(CY_SYS_CLK_SYSCLK_DIV8); //--> Provides a 24Mhz/DIV8 = 24/8 = 3 MHz clock. Lowest clock acceptable for SW Tx UART component.
// DEBUG_MSG(false, "\t\n After clkSelectReg CY_SYS_CLK_SYSCLK_DIV8=%u\n", CY_SYS_CLK_SELECT_REG);
// DEBUG_MSG(false, "CY_SYS_CLK_IMO_MIN_FREQ_MHZ / SYSCLK_DIVIDER / HFCLK_DIVIDER=%u\n", CY_SYS_CLK_IMO_MIN_FREQ_MHZ / SYSCLK_DIVIDER / HFCLK_DIVIDER);
// CySysFlashSetWaitCycles(CLK_IMO_MHZ / SYSCLK_DIVIDER / HFCLK_DIVIDER);
// Adjustment for CyDelay function
// CyDelayFreq(CLK_IMO_MHZ * HZ_IN_MHZ / SYSCLK_DIVIDER / HFCLK_DIVIDER);
// CySysFlashSetWaitCycles(CY_SYS_CLK_IMO_MIN_FREQ_MHZ / SYSCLK_DIVIDER / SYSCLK_DIVIDER / HFCLK_DIVIDER);
// Adjustment for CyDelay function
// DEBUG_MSG(false, "CY_SYS_CLK_IMO_MIN_FREQ_MHZ * HZ_IN_MHZ / SYSCLK_DIVIDER / HFCLK_DIVIDER=%u\n", CY_SYS_CLK_IMO_MIN_FREQ_MHZ * HZ_IN_MHZ / SYSCLK_DIVIDER / HFCLK_DIVIDER);
// CyDelayFreq(CY_SYS_CLK_IMO_MIN_FREQ_MHZ * HZ_IN_MHZ / SYSCLK_DIVIDER / SYSCLK_DIVIDER / HFCLK_DIVIDER); // to acheive 3Mhz must devide by 8
}
i remember i got it to work correctly where i can set the system to run on low power and restore it to full power if needed… but i can’t remember exactly what i did as i had to go through a lots of reading but the above should help you get there… if i have time i will trace my steps back and share them and if you get there before i do please share your findings.
here is one of the document i read to get there: https://community.infineon.com/gfawx74859/attachments/gfawx74859/psoc4/16113/1/cy_boot_v5_90_psoc4.pdf
cheers,
Jay